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ISAC TECHNOLOGY
Integrated Sensing & Communication Platform
5G/6G Heterogeneous Chiplet Architecture

Heterogeneous Chiplet Platform

Digital Die

  • TSMC 3nm/5nm
  • ARM Cortex-A78AE
  • 32 TOPs NPU
  • ISAC PHY Engine
  • 8-12W Power
UCIe Gen3
128 Gbps
<50ns latency

RF Die

  • 22nm/28nm RFSOI
  • 8T8R MIMO @ 28 GHz
  • Hybrid Beamforming
  • 2.4 GS/s ADC/DAC
  • 5-8W Power

Digital Baseband Chiplet

ARM Compute

  • 4× Cortex-A78AE @ 2.5 GHz
  • L1: 64KB I + 64KB D
  • L2: 1MB | L3: 4MB
  • 40 GFLOPS peak

NPU

  • 32 TOPs INT8
  • 512 MAC units (16×32)
  • 2MB weight buffer
  • TFLite, ONNX, PyTorch

ISAC PHY Processing Proprietary IP

Hardened RTL: OTFS/OFDM waveform gen | 2D FFT (256×128) | >95dB SIC | <500μs latency

RF & Analog Chiplet

TX/RX Chains

  • 8T8R @ 28 GHz
  • PA: +20 dBm output
  • LNA: 2.5dB NF
  • 40dB TX/RX isolation

Beamforming

  • 4 analog × 8 digital
  • 6-bit phase shifters
  • ±60° beam steering
  • <1μs switch time

Data Converters

ADC: 12-bit @ 2.4 GS/s | DAC: 14-bit @ 2.4 GS/s | PLL: 24-30 GHz, <100fs jitter

UCIe Gen3 Interconnect

128 Gbps
Bidirectional Bandwidth
<50ns
Die-to-Die Latency
32 GT/s
Raw Lane Rate
256B
Flit Size

ISAC Processing Pipeline

01
RF Acquisition
8-ch antenna → 2.4 GS/s ADC → 64 Gbps UCIe
02
OTFS-ISAC Dual Processing
Delay-Doppler → 2D FFT (256×128) → Parallel comm + sensing
03
Self-Interference Cancellation
64-tap LMS/RLS + PA model → >95dB suppression
04
AI-Enhanced Decision
32 TOPs NPU → Gesture + tracking → <1ms E2E

Memory Subsystem & Coherence

External Memory

  • DDR5-6400 (51.2 GB/s)
  • or HBM3 (900 GB/s)
  • ECC support (AES-256)
  • Memory encryption

On-Chip Memory

  • 16MB SRAM buffer
  • Low-latency access
  • ECC protected
  • Power optimized

Coherent CCI-500 Interconnect

ARM CoreLink CCI-500 cache coherent interconnect ensures data consistency across ARM cores, NPU, and ISAC PHY. Supports up to 4 ACE masters with full cache coherency protocol.

Software Stack & SDK

01
Operating System
Linux + RT patches (PREEMPT_RT) | Kernel 6.x | Real-time scheduling
02
SDK & Middleware
ISAC SDK (C/C++/Python) | AI Runtime (TFLite, ONNX) | 5G Protocol Stack
03
Firmware & Drivers
120K LOC: PHY control (50K) | NPU driver (30K) | RF cal (20K) | SIC (20K)
04
Development Tools
IDE plugins | Simulators | Profilers | Reference applications

System Connectivity & Interfaces

PCIe Gen4

  • x16 lanes @ 16 GT/s
  • 32 GB/s bidirectional
  • Host interface for data
  • Low-latency DMA

Ethernet

  • 10GbE / 25GbE
  • Time-sensitive networking
  • IEEE 1588 PTP sync
  • Industrial protocols

GPIO & Control

  • 32-bit GPIO banks
  • SPI, I2C, UART
  • Industrial I/O (24V)
  • Safety interlock signals

Debug & Test

  • JTAG debug interface
  • ARM CoreSight trace
  • Built-in self-test (BIST)
  • Temperature/voltage monitors

SIC Algorithm

🛡️

Self-Interference Cancellation

Trade Secret IP | >95dB Suppression

Hybrid analog (40dB) + digital (90dB) with 5th-order PA nonlinearity model. 64-tap LMS/RLS @ 1 MHz update, tracks ±500 Hz Doppler.

130dB total enables full-duplex <1m separation | <10μs convergence

OTFS-ISAC Waveform

📡

OTFS-ISAC Joint Waveform

Patent-Pending | Dual-Domain Processing

Delay-Doppler domain mapping achieves Doppler-invariant modulation. Optimized pilots serve dual-use: comm channel estimation + sensing reflection. Single 256×128 grid.

8dB SNR gain @ ±15 m/s vs OFDM | <-40dB sidelobe → multi-target resolution

Folded-CORDIC FFT

⚙️

Radix-2 DIF Folded-CORDIC

Hardware Accelerator | 10.2μs 2048-pt FFT

16-stage folded pipeline, 4 butterflies/cycle. Radix-2 DIF: 50% less memory access vs Radix-4. 32kB ROM for twiddle factors.

10.2μs @ 1.2 GHz | 180mW | 2.4mm² @ 3nm | 8× faster than ARM NEON

Event-Driven TinyML

🧠

Event-Driven TinyML Inference

Ultra-Low Power AI | <10ms Gesture

Pre-event detector (gas/acoustic threshold) wakes NPU on candidates only. INT8 models (1D-CNN, MLP). Multimodal fusion with hysteresis.

<250mW avg (90% reduction) | 94.7% accuracy | 8.3ms latency | <100μA sleep

Performance Specifications

50m
Sensing Range
0.1m Resolution
±15 m/s
Velocity Range
0.23 m/s Resolution
5 Gbps
Peak Throughput
@ 28 GHz FR2
<1ms
End-to-End Latency
Sensing → Action
130dB
Total SIC
40dB Analog + 90dB Digital
32 TOPs
AI Inference INT8
<10ms Latency

Competitive Advantages

Proprietary ISAC PHY IP

Joint waveform + dual-domain + >90dB SIC form competitive moat. Trade secrets protected.

Advanced-Node Edge

3nm/5nm enables 32 TOPs + <500μs latency impossible on older nodes. 40% power vs 7nm.

Cost-Optimized RF

22nm/28nm RF saves 60-70% silicon cost with superior analog. RF doesn't need <10nm.

UCIe Gen3 Expertise

128 Gbps + <50ns latency enables real-time coordination impossible with traditional interfaces.

Complete Turnkey Solution
120K+ LOC firmware + SDK = deploy ready, not just eval